The present invention relates to high density, multi-metal layer semiconductor device with reliable interconnection patterns. The present invention has particular applicability in manufacturing ultra large scale integration multi-metal layer semiconductor devices with a design rule of about 0.15 micron and under, e.g., about 0.12 micron and under.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require a design rule of about 0.15 micron and under, such as about 0.12 micron and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design rules to about 0.15 micron and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional semiconductor devices typically comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and patterned metal layers. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometries shrink into the deep submicron range.
A conductive plug filling a via opening is typically formed by depositing an inter-layer dielectric on a patterned conductive (metal) layer comprising at least one metal feature, forming an opening in the inter-layer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the inter-layer dielectric is removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via opening section in communication with an upper trench opening section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
The conventional practice of forming a landing pad completely enclosing the bottom surface of a contact or via utilizes a significant amount of precious real estate on a semiconductor ship which is antithetic to escalating demands for high density. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height/width of the through-hole opening. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a xe2x80x9cborderless viaxe2x80x9d, which also conserves chip real estate.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the resistance capacitance (RC) delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.15 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
As device geometries shrink and functional density increases, it becomes increasingly imperative to reduce the capacitance between metal lines. Line-to-line capacitance can build up to a point where delay time and cross talk may hinder device performance. Reducing the capacitance within multi-level metallization systems will reduce the RC constant, cross talk voltage, and power dissipation between the lines.
One way to increase the speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notable aluminum or an alloy thereof, and etching, or by damascene techniques where trenches are formed in dielectric layers and filled with conductive material. The use of metals having a lower resistivity than aluminum, such as copper, engenders various problems which limit their utility. For example, copper readily diffuses through silicon dioxide, the typical dielectric material employed in the manufacture of semiconductor devices, and adversely affects the devices. In addition, copper does not form a passivation film, as does aluminum. Hence, a separate passivation layer is required to protect copper from corrosion.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an inter-layer dielectric (ILD) spans from about 3.5 for dense silicon dioxide to over 8 for deposited silicon nitride and spin-on glass. Prior attempts have been made to reduce the interconnect capacitance and, hence, increase the integrated circuit speed, by developing dielectric materials having a lower dielectric constant than that of silicon dioxide. New materials having low dielectric constants, such as low dielectric constant polymers, e.g., methyl silsesquioxane (MSQ) and hydrogen silsesquioxane (HSQ), teflon, aerogels and porous polymers have been developed. There has been some use of certain polyimide materials for ILDs which have a dielectric constant slightly below 3.0.
Low dielectric constant (low-k) polymers, such as HSQ, offer many advantages for use in interconnect patterns. HSQ is relatively carbon free, thereby avoiding poison via problems. Moreover, due to the virtual absence of carbon, it is not necessary to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200xc2x0 C., but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400xc2x0 C. for intermetal applications and about 700xc2x0 C. to about 800xc2x0 C. for premetal applications.
However, low-k polymers, such as MSQ and HSQ, are susceptible to degradation during processing leading to various problems, such as voids, particularly when used as gap fill layers or ILDs during contact or via formations, particularly when forming borderless vias. For example, when forming a conventional contact or via a through-hole is etched through an ILD, e.g., HSQ, exposing surfaces forming the through-hole. When forming a borderless via, a photoresist mask is deposited and the misaligned through-hole etched to expose a portion of an upper surface and a portion of a side surface of a metal line, and penetrate into and expose the gap fill layer. The photoresist mask is then stripped, typically employing an oxygen (O2)-containing plasma. Subsequently, solvent cleaning is performed. It was found that the O2-containing plasma employed to strip the photoresist mask degrades low-k materials, such as HSQ, employed for ILDs and for gap fill layers when forming contacts and vias. After stripping a photoresist mask after forming a conventional contact or via opening, the low-k ILD is found to be degraded manifested by an increase in the dielectric constant of the low-k dielectric material. In addition, when employing a low-k dielectric material as a gap fill layer in forming a borderless via, upon subsequent filling of the misaligned through-hole, as with a barrier material, such as titanium nitride or titanium-titanium nitride, spiking occurs, i.e., the barrier material penetrates through the HSQ gap fill layer to the substrate or underlying conductive feature.
The precise mechanism involved in degrading low-k materials upon O2-plasma stripping of a photoresist mask after anisotropic etching to form a contact or via opening is not known with certainty, but would depend, in part, upon the particular low-k dielectric material employed for the ILD and/or gap fill layer. Various silsesquioxanes are particularly affected by O2-plasmas. For example, HSQ typically contains between about 70% and about 90% Sixe2x80x94H bonds. However, upon exposure to an O2-containing plasma, a considerable number of Sixe2x80x94H bonds are broken and Sixe2x80x94OH bonds are formed. Upon treatment with an O2-containing plasma, as much as about 20% to about 30% of the Sixe2x80x94H bonds in the deposited HSQ film remained. In addition, it was found that exposure to an O2-containing plasma increased the moisture content of the as deposited HSQ film and its propensity to absorb moisture. An HSQ film having reduced Sixe2x80x94H bonds and high Sixe2x80x94OH bonds tends to absorb moisture from the ambient, which moisture outgasses during subsequent barrier metal deposition. Thus, it was found that during subsequent barrier and metal deposition, e.g., titanium-titanium nitride and tungsten, outgassing occurred thereby creating voids leading to incomplete electrical connection.
Solis, et al. in xe2x80x9cNovel CF4+H2O Ashing Process for Reduction of Via Resistancexe2x80x9d, ISSM Proceedings, 1997, pages F-25 through F-27, disclose the use of ashing chemistry incorporating H2O and CF4 for improved polymer stripability and reduced via resistance. Solis, in U.S. Pat. No. 5,851,302, discloses the use of a plasma containing CF4 and H2O for stripping sidewall polymer from etched via holes and from etched metal lines. Solis et al., in U.S. Pat. No. 5,814,155, disclose the use of a plasma containing O2, CF4 and H2O for ashing to selectively remove sidewall polymer formation from etched metal lines.
In copending U.S. patent application Ser. No. 08/933,430, filed on Dec. 18, 1997, a method is disclosed for selectively heating portions of a deposited HSQ layer adjoining a metal feature to increase the resistance of such adjoining portions to penetration when etching a misaligned through-hole for a borderless via. In copending U.S. patent application Ser. No. 08/933,125, filed on Dec. 18, 1997, a method is disclosed for preventing the degradation of deposited HSQ layers during formation of a borderless via comprising stripping the photoresist mask employing a hydrogen-containing stripping plasma to prevent reduction in the number of Sixe2x80x94H bonds of the deposited HSQ gap filled layer below about 70%.
In view of the manifest advantages attendant upon employing low-k materials, such as HSQ, in interconnection systems, as for ILDs and gap fill layers, there exists a need to provide efficient methodology enabling such use of low-k materials without degradation.
An advantage of the present invention is a method of manufacturing a high density multi-metal layer semiconductor device with a design rule of about 0.15 micron and under, and an interconnection pattern comprising high integrity contact/vias and low-k materials without degradation.
Another advantage of the present invention is a method of forming interconnection patterns employing low-k materials for ILDs and/or gap fill layers without degradation upon forming contact/vias.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer on a substrate; forming a first patterned conductive layer having gaps on the first dielectric layer, the first patterned conductive layer comprising a first conductive feature having an upper surface and side surfaces; depositing a dielectric gap fill layer to fill the gaps; depositing a second dielectric layer on the first patterned conductive layer and on the gap fill layer; forming a photoresist mask on the second dielectric layer; forming a through-hole in the second dielectric layer exposing the upper surface of the first conductive feature; and removing the photoresist mask employing a water vapor-containing plasma; wherein, the gap fill layer and/or second dielectric layer have an as-deposited dielectric constant no greater than about 3.
Another advantage of the present invention is a method of manufacturing a semiconductor device, the method comprising: depositing a layer of dielectric material, having an as-deposited dielectric constant no greater than about 3, over a conductive region or conductive feature; forming a through-hole in the dielectric layer exposing the upper surface of the conductive region or conductive feature; and removing the photoresist mask with a water vapor-containing plasma.
Embodiments of the present invention include the use of a low-k dielectric material, e.g., a dielectric material having a dielectric constant of about 1.8 to about 3.0, as an ILD and/or gap fill layer, and removing the photoresist mask employing a water vapor-containing plasma at a removal rate of about 10,000 to about 20,00 xc3x85/min such that the dielectric constant of the low-k material does not increase more than about 10%. Embodiments of the present invention comprise employing a silsesquioxane, such as HSQ, as an ILD and/or gap fill layer and removing the photoresist mask with a water vapor-containing plasma at a rate of about 10,000 to about 20,000 xc3x85/min such that the number of Sixe2x80x94H bonds in the HSQ layer is not reduced below about 70% of the number of Sixe2x80x94H bonds in the as-deposited HSQ layer.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.